A3 Digital If Assembly Theory Of Operation - Keysight n9020a Service Manual

Mxa signal analyzer
Hide thumbs Also See for n9020a:
Table of Contents

Advertisement

Analog/Digital IF Troubleshooting
40 MHz BW IF Section

A3 Digital IF Assembly Theory of Operation

Refer to
NOTE
Data Acquisition
Rear Panel Triggers
DSP
Reconstruction
Chapter 11, "Block
The 22.5 MHz IF comes from the A2 Analog IF assembly. The input level to
the A3 Digital IF assembly is −25 dBm when observing the 50 MHz
calibrator signal. The IF input has a 25 MHz bandwidth centered at 22.5
MHz. The analog circuitry leading to the ADC converts the singled ended
signal from the Analog IF to differential required by the ADC. In addition, it
is part of a filter, part of which is on the AIF, which improves distortion.
Finally, it couples in the dither signal. The ADC is a 16 bit device sampling
continuously at 100 Ms/second.
The 250 MHz IF comes from the A15 Front End Control assembly. The input
level is approximately -25 dBm when observing the 50 MHz calibrator
signal. The IF input has a 40 MHz bandwidth centered at 250 MHz. The
analog circuitry leading to the ADC converts the single-ended signal from
the Front End Control to differential required by the ADC. Finally, it couples
in the dither signal. The ADC is a 12-bit device sampling continuously at
200 Ms/second.
The board has two trigger inputs and two trigger outputs all used via BNC
connectors on the rear panel. The trigger inputs are used when an external
device has a trigger signal and the user wants to use that external trigger to
trigger the signal analyzer. The trigger outputs are used to synchronize
other pieces of test equipment to the analyzer. These outputs are
configurable through the Input/Output menu via the front panel of the
instrument.
The trigger inputs each allow trigger levels to be set from −5 to +5 volts
using the control DAC. The circuits have relatively high input impedance.
The trigger outputs have 50 Ω source impedance with TTL drive levels into
no load.
The outputs of the ADCs go to the T2 digital FPGA. T2 links the ADC with
memory and the Feldspar DSP. T2 does all the swept SA DSP and
orchestrates measurements. It also provides outputs to the reconstruction
system. Feldspar is a DPSP ASIC which performs all the DSP for wide-band
applications.
Diagrams".
263

Advertisement

Table of Contents
loading

This manual is also suitable for:

X seriesN9020a

Table of Contents