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•
End-of-block-transfer interrupts
•
Triggering from interrupt lines and all peripherals
1.4.6
PLL-based Clock Oscillator
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs
clock input division, frequency multiplication, and skew elimination; and the clock generator (CLKGEN),
which performs low-power division and clock pulse generation. PLL-based clocking:
•
Allows change of low-power divide factor (DF) without loss of lock
•
Provides output clock with skew elimination
•
Provides a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16), and a
power-saving clock divider (2
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input. This feature offers two immediate benefits:
•
A lower frequency clock input reduces the overall electromagnetic interference generated by a
system.
•
The ability to oscillate at different frequencies reduces costs by eliminating the need to add
additional oscillators to a system.
1.4.7
JTAG TAP and OnCE Module
The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the
Standard Test Access Port and Boundary Scan Architecture
circuit boards led to developing this standard under the sponsorship of the Test Technology Committee of
IEEE and JTAG. The DSP56300 core implementation supports circuit-board test strategies based on this
standard.
The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and three test data
registers. A boundary scan register links all device signals into a single shift register. The test logic,
implemented utilizing static logic design, is independent of the device system logic. More information on
the JTAG port is provided in
The OnCE module provides a nonintrusive means of interacting with the DSP56300 core and its
peripherals so a user can examine registers, memory, or on-chip peripherals. This facilitates hardware and
software development on the DSP56300 core processor. OnCE module functions are provided through the
JTAG TAP signals. More information on the OnCE module is provided in
On-Chip Emulation Module
1.4.8
On-Chip Memory
The memory space of the DSP56300 core is partitioned into program memory space,
X data memory space, and Y data memory space. The data memory space is divided into X and Y data
memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data
Freescale Semiconductor
i
: i = 0 to 7) to reduce clock noise
DSP56300 Family Manual, JTAG Port
.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
DSP56300 Core Functional Blocks
. Problems associated with testing high-density
.
DSP56300 Family Manual,
IEEE 1149.1
1-7
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