Table of Contents
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Revision history
Chapter
Chapter 6
Performance Optimization
Chapter 7
e200z4 Core
Chapter9
Multi-Layer AHB Crossbar Switch
(XBAR)
Chapter 10
Peripheral Bridge (PBRIDGE)
Chapter 11
Flash memory
Chapter 12
SRAM
Chapter 13
Memory Protection Unit (MPU)
1714
Table A-3. Changes between revisions 2 and 3
• New chapter
• MMU is 24-entry (was 16-entry)
• Instruction cache is 8_KB (was incorrectly stated as 4_KB)
• Supports WAIT power-saving mode (previously incorrectly stated DOZE,
NAP and SLEEP modes were also supported)
• XBAR device-specific block diagram: Replaced z446n3 with e200z4
• Master/Slave mappings: Replaced z446n3 with e200z4
• Previously there were no control registers for the peripheral bridge. Registers
added: Master Privilege Control Register (MPCR), Peripheral Access Control
Registers (PACR) and Off-Platform Peripheral Access Control Registers
(OPACR).
Added UTn registers to memory map
MCR field description:
• Removed references to "Tdone" and "Tres" from DONE field description
• Removed references to "Tpsus" from PSUS field description
• Removed references to "Tesus" from ESUS field description
Updated Flash memory map
Added UMISR[0:4] registers
Footnote added warning that flash configuration registers must not be written by
software executing from flash memory.
• Detail on Standby SRAM power sources added to Standby Mode section
Changes to MPU RGD Alternate Access Control n (MPU_RGDAACn)
• Four new fields added; M7RE, M7WE, M6RE and M6WE
• Three fields deleted: M1PE, M1SM, M1UM and M0PE
Warning added to Application Information section discussing errors caused by
application code that crosses MPU region boundaries.
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
Freescale Semiconductor
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