NXP Semiconductors MPC5644A Reference Manual page 1733

Table A-6. Changes between revisions 5 and 6 (continued)
Chapter
Enhanced Queued
Analog-to-Digital Converter
(EQADC)
Decimation Filter
Deserial Serial Peripheral
Interface
Enhanced Serial Communication
Interface
FlexCAN Module
JTAG Controller
Freescale Semiconductor
In Section 25.2.2, Block
• Added foot note "Decimation filters A and B and Reaction module".
• Added information about Decimation filters A and B and about reaction
module.
• In Section 25.6.5.2, Distributing Result Data into RFIFOs
about Decimation filters A and B and about reaction module.
• In Section 26.4.2.3, Decimation Filter Module Extended Configuration
Register (DECFILTER_MXCR)/Table 26-12
For bits SZROSEL[1:0], SRQSEL[2:0] and SENSEL[1:0] the note is:
—The hardware input signals are ZSELA for Decimation filter A and ZSELB
fractionation filter B
For bit SHLTSEL[1:0] the note added is:
—The hardware input signals are HSELA for Decimation filter A and HSEB
for Decimation filter B.
• Updated Section 26.5.10, Soft-reset command description
• In Section 30.8.2.11, DSPI DSI Configuration Register (DSPI_DSICR)
DMS,PES,PE,PP bits in DSPI_DSICR register.
• Added the following registers
—DSPI Hardware Configuration Register (DSPI_HCR)
—DSPI DSI Serialization Source Select Register (DSPI_SSR)
—DSPI DSI Parallel Input Select Register 0 (DPSI_PISR0)
—DSPI DSI Parallel Input Select Register 1 (DPSI_PISR1)
—DSPI DSI Parallel Input Select Register 2 (DPSI_PISR2)
—DSPI DSI Parallel Input Select Register 3 (DPSI_PISR3)
—DSPI DSI Deserialized Data Interrupt Mask Register (DSPI_DIMR)
—DSPI DSI Deserialized Data Polarity Interrupt Register (DSPI_DPIR)
• Updated Figure 31-4 (Control register 2
"BRK13" to "BRCL"
"BESM13" to "BESM"
"SBSTP" to "BESTP".
• Updated Figure 31-5 (SCI data register (eSCI_DR))
"R8" to "RN"
"R" to "RD[11:8]".
• Updated Section 31.4.5.3.4, Single wire mode
TXDIR bit (eSCI_CR2[1]) determines whether the TXD pin is going to be
used as an input (TXDIR= 0) or an output (TXDIR = 1) in this mode of
operation".
• Updated the entire Section 31.3, Memory map and register
• In Section 31.3.2.2, Control register 1 (eSCI_CR1)
bits 16-31 to Read/Write.
• In Section 31.3.2.2, Control register 1 (eSCI_CR1)
bits 21 to read only.
• Table 32-12 (ESR Register field descriptions)
"Field"
TXWRN to "TX Error Warning"
RXWRN to "RX Error Warning".
• Section 32.4.5.8, Error and Status Register
"The CPU read action clears bits 16–23" to "The CPU read action clears bits
16–21".
Section 36.4.1.1, Instruction Register/Figure 36-2 (5-bit Instruction Register)
changed the Reset value 00001.
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
diagram:
added two notes:
(eSCI_CR2))by changing bit
by removing the text "The
updated the "Description" for
(ESR). Changed the text from
Revision history
added information
added
by changing bit
definition.
changed the access of
changed the access of
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