Table of Contents
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Revision history
Table A-4. Changes between revisions 3 and 4 (continued)
Chapter
Chapter 24
Reaction Module
Chapter 26
Decimation Filter
Chapter 28
System Information Module and
Trim (SIM)
1726
REACM Channel n Configuration Register (REACM_CR) renamed to
REACM_CHCRn
REACM Channel n Status Register (REACM_SR) renamed to REACM_CHSRn
REACM Channel n Router Register (REACM_RR) renamed to
REACM_CHRRn
Updates to "Threshold Bank and Comparator" section:
• Changed formula for second comparison to:
"COMP = ADC_DATA >= THRESHOLD_VALUE[THRESPT + 1]" (was ">="
instead "<")
• In block diagram, changed "SKy-Blue or eTPU" to "XBAR Master or eTPU".
Changes to REACM_GEFR register:
• Added SQER and RAER to list of flags that could cause EFn to be set
• Added EF5 field
Changes to REACM_CHCRn register:
• DMAEN field added
• Note added: If the DOFF value is changed just after the channel is enabled,
it is not assured the new DOFF value is immediately used in the channel
output.
Changes to REACM_STBK register:
• Note added to SHARED_TIMER field: When using the shared timer for
sequence advance, the counted time (considering prescaler) must be greater
than 64 clock cycles.
Changes to REACM_HOBK register:
• Note added to HOLD_OFF field: When using the hold-off timer for sequence
advance, the counted time (considering prescaler) must be greater than 64
clock cycles.
New subsection added to ADC Interface section: Input Buffer Overrun
Deleted "No Modulation Mode" section
Added information in Debug Mode description
Deleted Threshold Bank section
DMA Support section added
Correction: there are 3 shared timers implemented (was 16)
Memory map updated
Reformatted register information
Renamed chapter (formerly Flash Fuse Loader (FFL))
Added description of unique device ID
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
Freescale Semiconductor
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