Table of Contents
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Revision history
Table A-2. Changes between revisions 1 and 2 (continued)
Chapter
Chapter 8
Multi-Layer AHB Crossbar Switch
(XBAR)
Chapter 10
Flash
Chapter 11
SRAM
Chapter 12
Memory Protection Unit (MPU)
Chapter 14
Interrupt Controller (INTC)
1704
• Master Port functionality and Slave Port functionality sections deleted
• Detail added to SGPCR[PARK] description
• MPR[MSTRx] descriptions updated with port functions
• Parking section added
• HLP bit removed from SGPCR register. It has no effect
• Register summary removed.
• MPRn register reset value is now 0x43020010
Removed following bits from XBAR_SGPCRn registers (ports controlled by this
bits do not exist on this device):
• HPE6
• HPE5
• HPE4
• HPE3
• HPE1
Register names changed:
• CR register renamed to MCR
• LML register renamed to LMLR
• HBL register renamed to HLR
• SLL register renamed to SLMLR
• LMS register renamed to LMSR
• HBS register renamed to HSR
• ADR register renamed to AR
• PFCR1 register renamed to BIUCR
• PFAPR register renamed to BIUAPR
• PFCR2 register renamed to BIUCR2
Register field value definitions:
• BIUAPR[MnAP] values table updated with correct master port information
• BIUCR[MnPFE] values table updated with correct master port information
Registers added:
• UT0-UT2
• UM0-UM4
Flash segmentation diagram and memory map updated
• Note about MUDCR register and reference to ECSM chapter adde.d
• Added a section on initialization
New chapter
• PCR_SELx fields removed from INTC_PSR register maps.
• Interrupt vector 307 is sourced by MCM (mcm_ipi_ecc_1bit_int) and is
source of both flash and SRAM single-bit ECC error correction.
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
Freescale Semiconductor
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