Table of Contents
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Revision history
A.6
Changes between revisions 5 and 6
Chapter
Introduction
Signal Description
Operating Modes and Clocking
Device Performance Optimization
1730
Table A-6. Changes between revisions 5 and 6
• Removed references of "MPC5634M and SPC563M64" from
MPC5644A and MPC5642A Device
• In
Table 1-1 (MPC5644A and MPC5642A comparison)
"MPC5642A" done the following changes:
—For row "Packages" removed text "Known Good DIe(KGD)".
—For row "External bus" added value 4 128-bit.
—For row "Calibration bus" changed the value to "None".
• Changed
Table 1 (MPC5644A signal
—in row "RESET" column "Status/During Reset" changed the value from
"RESET / Up" to "— / Up".
—in row "RSTOUT" column "Status/During Reset" changed the value from
"RSTOUT /Down" to "RSTOUT / Low".
—in row "RSTOUT" column "Status/After Reset" changed the value from
"RSTOUT/Down" to "RSTOUT /High".
—in row "PLLREF" column "Status/During Reset" changed the value from "—
/Up" to "PLLREF/UP" and column "Status/After Reset" changed from
"PLLREF/UP" to "— /Up".
—in row "BOOTCFG[0]" column "Status/During Reset" changed the value
from "— /Down" to "BOOTCFG[0]/Down" and column "Status/After Reset"
changed from "BOOTCFG[0]/Down" to "— /Down".
—in row "BOOTCFG[1]" column "Status/During Reset" changed the value
from "— /Down" to "BOOTCFG[1]/Down" and column "Status/After Reset"
changed from "BOOTCFG[1]/ Down" to "— /Down".
—in row "WKPCFG" column "Status/During Reset" changed from "— /Up" to
"WKPCFG/UP" and column "Status/After Reset" changed from
"WKPCFG/UP" to "— /Up".
• Updated
Table 2 (Pad types)
• Updated text of
Section 5.3.3.1, Support for 150 MHz system clock
generation
to "A possible PLL configuration is shown below:
• Input clock (crystal frequency): 40 MHz
• EPREDIV/IDF divider = /8 (1–15 range supported)
• EMFD/NDIV loop divider = 60 (32–96 supported)
• VCO clock out = 300 MHz (256–512 MHz range supported)
• ERFD/ODF output divider = /2 (/2, /4, /8, /16 supported)".
• Updated the following texts of
clock generation
to
• EPREDIV/IDF divider = /8 (1–15 range supported)
• ERFD/ODF output divider = /4 (/2, /4, /8, /16 supported).
• Changed the Note of
"The CLKOUT pin is only available in the 208- and 324-pin packages" to "The
CLKOUT pin is only available in the 324-pin package".
• Changed bit 27 in
Figure 6-2 (L1 Cache Control and Status Register 1
(L1CSR1))
from "0" to "ICORG".
• Added Description for "ICORG" bit.
• Removed instance of z7 from
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
Comparison.
properties).
by hiding the "Name" column.
Section 5.3.3.2, Support for 100 MHz system
Section 5.3.4.6.2, External Bus Clock (CLKOUT)
Section 6.3.4.2, Recommended configuration
Section 1.2,
for column
from
Freescale Semiconductor
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