Table of Contents
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Chapter
Chapter 3
Signal Description
(cont)
Chapter 4
Resets
Chapter 5
Operating Modes and Clocking
Freescale Semiconductor
Table A-3. Changes between revisions 2 and 3
Signal Details table updated:
• Added eTPU2 reaction channels
• Changed IRQ[0:15] to two ranges, excluding IRQ6, which does not exist on
this device
• Changed TCR_A to TCRCLKA (TCR_A is the pin name, not the signal name)
• Changed WE_BE[0:1] to WE_BE[0:3] (2 new signals added to Rev. 2). Also
changed notation from "WE_BE[n]" to "WE[n]/BE[n]" to be consistent.
Changes to Power/ground segmentation table:
• ADDR[20:21] removed from VDDE2 segment; they are in VDDE-EH
• CAL_CS1 removed from VDDE12 segment (there is no CAL_CS1 on this
device)
• CAL_EVTO and CAL_MCKO removed from VDDE12 segment. Those pins
do not exist
• VDDE-VDDEH renamed to VDDE-EH
• EMIOS24 removed from VDDEH segment. That pin does not exist.
• ETPUA[0:9] added to VDDEH4 segment
• Renamed TCR_A in VDDEH4 segment to TCRCLKA.
• EXTAL and XTAL added to VDDEH6 segment
• AN15-FCK added to VDDEH7 segment
• GPIO98, GPIO99, GPIO206, GPIO207 and GPIO219 added to VDDEH7
segment.
• MSEO1 added to VDDEH7 segment
Most of chapter updated
• Max clock speed is now 150 MHz (was 145 MHz)
• EPREDIV/IDF divider = /7 for 150 MHz clock (was /8 for 145 MHz clock)
• EMFD/NDIV loop divider = 60 for 150 MHz clock (was 58 for 145 MHz clock)
• VCO clock out = 266.67 MHz for 150 MHz clock (was 290 MHz for 145 MHz
clock)
• ERFD/ODF output divider = /1 for 150 MHz clock (was /2 for 145 MHz clock)
• EPREDIV/IDF divider = /7 for 100 MHz clock (was /4)
• EMFD/NDIV loop divider = 80 for 100 MHz clock (was 40)
• ERFD/ODF output divider = /1 for 100 MHz clock (was /4)
• Editorial and formatting changes
• Changed field name PLLCFG to CLKCFG in
with crystal reference
reference
• Replaced text of footnote defining OCR register with reference to the
ez200z4 core reference manual.
•
Section 5.4.4.6, "Clock
• Changed "The MCU provides four clock dividers" to "The MCU provides five
clock dividers"
• Editorial changes
• Added explanation of how SYSDIV programming depends on values of fields
BYPASS and SYSCLKDIV in SIU_SYSDIV register
•
Section 5.4.4.6.4, "Engineering Clock Divider
"according to the below mentioned equation" from first paragraph (no
equation present)
•
• Replaced text of footnote defining OCR register with reference to the
ez200z4 core reference manual.
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
Section 5.4.4.1, "Bypass mode
and
Section 5.4.4.2, "Bypass mode with external
dividers:
(ENGDIV): Removed phrase
Revision history
1713
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