NXP Semiconductors MPC5644A Reference Manual page 1681

Bit Name
15 LP_DBG_E Low Power Debug Enable
N This bit enables debug functionality on exit from low power modes on supported devices.
1 = Low power debug enabled
0 = Low power debug disabled
14:1 — Reserved
0
9:8 LPn_SYN Low Power Mode n Synchronization
These bits are used to synchronize the entry into low power modes between the device and
debug tool. Supported devices set these bits before a pending entry into low power mode. After
reading the bit as set, the debug tool then clears the bit to acknowledge to the device that it
may enter the low power mode.
1 = Low power mode entry pending
0 = Low power mode entry acknowledged
7:1 — Reserved
0 PSTAT_EN Processor Status Mode Enable
This bit enables processor status (PSTAT) mode. In PSTAT mode, all auxiliary output port MDO
pins are used to transmit processor status information, and Nexus messaging is unavailable.
1 = PSTAT mode enabled
0 = PSTAT mode disabled
1
PSTAT Mode is intended for factory processor debug only. The PSTAT_EN bit should be written to disable PSTAT
mode if Nexus messaging is desired. No Nexus messages are transmitted under any circumstances when PSTAT
mode is enabled.
1
The SYS_CLK setting for MCKO frequency should only be used if this setting does not violate the
maximum operating frequency of the auxiliary port pins.
Freescale Semiconductor
Table 37-6. PCR field descriptions (continued)
1
Table 37-7. MCKO_DIV values
MCKO_DIV[2:0]
0
1
2
3
4
5
6
7
MPC5644A Microcontroller Reference Manual, Rev. 6
Description
MCKO frequency
1
SYS_CLK
SYS_CLK/2
SYS_CLK/3
SYS_CLK/4
Reserved
Reserved
Reserved
SYS_CLK/8
Nexus Port Controller (NPC)
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