NXP Semiconductors MPC5644A Reference Manual page 1711

A.3 Changes between revisions 2 and 3
Chapter
Chapter 1
Introduction
Chapter 2
Memory Map
Freescale Semiconductor
Table A-3. Changes between revisions 2 and 3
Updated several instances of text to indicate 8 KB instruction cache (was
incorrectly stated as 4 KB)
Updates to device comparison:
• Max clock speed for device is 150 MHz (was 145 MHz)
Updates to features list:
• Core clock speed for device is 150 MHz (was 145 MHz)
• Correction: there are 6 reaction channels (noted as 5)
• Development Trigger Semaphore (DTS) added to features list and feature
details
• FlexRay now has 128 message buffers and ECC support
• "Allocated Size" for reserved area from 0x4003_0000 to 0xBFFF_FFFF
changed to 2 GB - 192 KB.
• Range from 0xFFF0_0000 to 0xFFF0_3FFF is no longer reserved—it is
allocated to PBRIDGE (AIPS-lite) registers
• Reaction Module (REACM) registers added at starting address
0xC403_0000. This space was previously reserved. There is reserved space
before and after these registers.
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
Revision history
1711