NXP Semiconductors MPC5644A Reference Manual page 1720

Revision history
Chapter
Chapter 34
FlexRay Module
Chapter 38
Development Trigger Semaphore
(DTS)
1720
Table A-3. Changes between revisions 2 and 3
ECC has been added to the PE DRAM memory
• Single-bit Error Detection and Correction
• Multi-bit Error Detection
ECC has been added to the CHI LRAM memory
• Single-bit Error Detection
• Multi-bit Error Detection
Module now has 128 message buffers (was 64)
New sections added:
• "Controller Host Interface Clocking"
• "System Bus Access"
• "PE Data Memory (PE DRAM)"
• "CHI Lookup-Table Memory (CHI LRAM)"
• "Memory Content Error Detection"
Memory management content added to Application Information section.
New registers added:
• FR_PEDRAR
• FR_PEDRDR
• FR_EEIFER
• FR_EERICR
• FR_EERAR
• FR_EERDR
• FR_EERCR
• FR_EEIAR
• FR_EEIDR
• FR_EEICR
New chapter
MPC5644A Microcontroller Reference Manual, Rev. 6
Changes
Freescale Semiconductor