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5.2.2
Clock Generation Circuit Function and Operaion
The clock generation circuit generates the CPU clock (
and controls the CPU operating mode, such as standby mode etc.
Clock generation circuit operation is determined by the processor clock control register (PCC).
Upon RESET input, the PCC is cleared to 0000 and the PD75402A operates in low-speed mode (15.3 s: when
operating at 4.19 MHz).
Peripheral hardware is supplied with various clocks scaled from the system clock generation circuit output (f
in the case of crystal/ceramic oscillation, and f
From this section on, only f
should be replaced by f
.
X
The operation of each block is described below.
(1) Processor clock control register (PCC)
The PCC is a 4-bit register which performs selection of the CPU clock
The format of the PCC is shown in Fig. 5-11.
When bit 3 or bit 2 is set (1), standby mode is selected. When standby mode is released by the Standby Release
signal, both bits are automatically cleared and the normal operating mode is reestablished (see CHAPTER 7
"STANDBY FUNCTION" for details).Setting of the low-order 2 bits of the PCC is performed by a 4-bit memory
handling instruction. At this time, ensure that bits 3 and 2 are reset to "0" so that the pattern "00
Bits 3 and 2 are set (1) by the STOP instruction and the HALT instruction respectively.
RESET input clears the PCC to 0000.
Example
1.
To set the machine cycle to 0.95 s (f
SEL
MOV
MOV
2.
To set the machine cycle to 1.63 s (f
SEL
MOV
MOV
3.
To select the STOP mode. (Be sure to include an NOP instruction after a STOP or HALT instruction.)
STOP
NOP
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
when an external clock is used) by the frequency divider.
X
is used when expressing the speed of the various clocks; for an external clock, this
XX
= 4.19 MHz).
XX
MB15
A, #0011B
PCC, A
= 4.91 MHz).
XX
MB15
A. # 0010B
PCC, A
) and various clocks for supply to peripheral hardware,
and control of the CPU operating mode.
XX
" is written.
55
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