Clock Output Control Circuit Configuration; Clock Output Function Control Registers; Clock Output Control Circuit Block Diagram - NEC PD78056F User Manual

12.2 Clock Output Control Circuit Configuration

The clock output control circuit consists of the following hardware.
Control register
Figure 12-2. Clock Output Control Circuit Block Diagram
f
XX
f /2
XX
2
f /2
XX
3
f /2
XX
4
f /2
XX
5
f /2
XX
6
f /2
XX
7
f /2
XX
f
XT
CLOE TCL03 TCL02 TCL01 TCL00

12.3 Clock Output Function Control Registers

The following two types of registers are used to control the clock output function.
• Timer clock select register 0 (TCL0)
• Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TCL0 to 00H.
Remark Besides setting PCL output clock, TCL0 sets the 16-bit timer register count clock.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
Table 12-1. Clock Output Control Circuit Configuration
Item
Timer clock select register 0 (TCL0)
Port mode register 3 (PM3)
Synchronizing
Circuit
4
Timer Clock Select Register 0
Internal Bus
Configuration
P35
Output Latch
PCL /P35
PM35
Port Mode Register 3