Rom Correction Control Registers; Correction Control Register Format - NEC PD78056F User Manual

25.3 ROM Correction Control Registers

The ROM correction is controlled with the correction control register (CORCN).
(1) Correction control register (CORCN)
This register controls whether or not the correction branch request signal is generated when the fetch
address matches the correction address set in correction address registers 0 and 1. The correction control
register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0,
CORST1). The correction enable flags enable or disable the comparator match detection signal, and
correction status flags show the values are matched.
CORCN is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CORCN to 00H.
Symbol 7 6 5
CORCN 0 0 0
Note Bits 0 and 2 are read-only bits.
CHAPTER 25 ROM CORRECTION
Figure 25-3. Correction Control Register Format
4 3 2 1 0
0 COREN1 CORST1 COREN0 CORST0
After
Address
Reset
00H
FF8AH
CORST0
Correction address register 0 and fetch address match detection
0 Not detected
1 Detected
Correction address register 0 and fetch address match
COREN0
detection control
Disabled
0
1 Enabled
CORST1
Correction address register 1 and fetch address match detection
Not detected
0
1 Detected
Correction address register 1 and fetch address match
COREN1
detection control
0 Disabled
Enabled
1
R/W
Note
R/W
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