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TCL13 TCL12 TCL11 TCL10
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Other than above
Remarks 1. f
X
2. MCS
3. TCL10 to TCL13 : Bits 0 to 3 of timer clock selection register 1 (TCL1)
4. Values in parentheses when operated at f
226
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS
Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time
Minimum Interval Time
MCS = 1
MCS = 0
TI1 input cycle
TI1 input cycle
2
2
1/f
2
1/f
X
X
(400 ns)
(800 ns)
2
3
2
1/f
2
1/f
X
X
(800 ns)
(1.6 s)
3
4
2
1/f
2
1/f
X
X
(1.6 s)
(3.2 s)
4
5
2
1/f
2
1/f
X
X
(3.2 s)
(6.4 s)
5
6
2
1/f
2
1/f
X
X
(6.4 s)
(12.8 s)
6
7
2
1/f
2
1/f
X
X
(12.8 s)
(25.6 s)
7
8
2
1/f
2
1/f
X
X
(25.6 s)
(51.2 s)
8
9
2
1/f
2
1/f
X
X
(51.2 s)
(102.4 s)
9
10
2
1/f
2
1/f
X
X
(102.4 s)
(204.8 s)
11
12
2
1/f
2
1/f
X
X
(409.6 s)
(819.2 s)
Setting prohibited
: Main system clock oscillation frequency
: Bit 0 of oscillation mode selection register (OSMS)
Maximum Interval Time
MCS = 1
MCS = 0
8
2
TI1 input cycle
8
2
TI1 input cycle
9
10
2
1/f
2
1/f
X
X
(102.4 s)
(204.8 s)
10
11
2
1/f
2
1/f
X
X
(204.8 s)
(409.6 s)
11
12
2
1/f
2
1/f
X
X
(409.6 s)
(819.2 s)
12
13
2
1/f
2
1/f
X
X
(819.2 s)
(1.64 ms)
13
14
2
1/f
2
1/f
X
X
(1.64 ms)
(3.28 ms)
14
15
2
1/f
2
1/f
X
X
(3.28 ms)
(6.55 ms)
15
16
2
1/f
2
1/f
X
X
(6.55 ms)
(13.1 ms)
16
17
2
1/f
2
1/f
X
X
(13.1 ms)
(26.2 ms)
17
18
2
1/f
2
1/f
X
X
(26.2 ms)
(52.4 ms)
19
20
2
1/f
2
1/f
X
X
(104.9 ms)
(209.7 ms)
= 5.0 MHz.
X
Resolution
MCS = 1
MCS = 0
TI1 input edge cycle
TI1 input edge cycle
2
2
1/f
2
1/f
X
X
(400 ns)
(800 ns)
2
3
2
1/f
2
1/f
X
X
(800 ns)
(1.6 s)
3
4
2
1/f
2
1/f
X
X
(1.6 s)
(3.2 s)
4
5
2
1/f
2
1/f
X
X
(3.2 s)
(6.4 s)
5
6
2
1/f
2
1/f
X
X
(6.4 s)
(12.8 s)
6
7
2
1/f
2
1/f
X
X
(12.8 s)
(25.6 s)
7
8
2
1/f
2
1/f
X
X
(25.6 s)
(51.2 s)
8
9
2
1/f
2
1/f
X
X
(51.2 s)
(102.4 s)
9
10
2
1/f
2
1/f
X
X
(102.4 s)
(204.8 s)
11
12
2
1/f
2
1/f
X
X
(409.6 s)
(819.2 s)
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