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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES)
(3) Other signals
Figure 16-33 shows RELT and CMDT operations.
SO0 Latch
RELT
CMDT
(4) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start.
2. It is necessary to set the N-ch open-drain output in the high impedance state when
receiving data, so write FFH in SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit
(match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is
tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged
to have occurred.
Figure 16-33. RELT and CMDT Operations
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