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(5) Square-wave output
TM0 can output a square wave with any selected frequency.
Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width
MCS = 1
MCS = 0
2
TI00 input cycle
2
—
(400 ns)
2
2
1/f
2
X
(400 ns)
(800 ns)
2
3
2
1/f
2
X
(800 ns)
(1.6 s)
3
4
2
1/f
2
X
(1.6 s)
(3.2 s)
2
watch timer output cycle
Remarks 1. f
: Main system clock oscillation frequency
X
2. MCS: Bit 0 of oscillation mode selection register (OSMS)
3. Values in parentheses when operated at f
(6) One-shot pulse output
TM0 is able to output one-shot pulse which can set any width of output pulse.
8.3 16-Bit Timer/Event Counter Configuration
The 16-bit timer/event counter consists of the following hardware.
Timer register
Register
Timer output
Control register
Note Refer to the Figure 21-1 Basic Configuration of Interrupt Function.
174
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Maximum Pulse Width
MCS = 1
16
2
TI00 input cycle
1/f
X
—
16
1/f
2
1/f
X
X
(13.1 ms)
17
1/f
2
1/f
X
X
(26.2 ms)
18
1/f
2
1/f
X
X
(52.4 ms)
16
2
watch timer output cycle
Table 8-4. 16-Bit Timer/Event Counter Configuration
Item
16 bits
1 (TM0)
Capture/compare register: 16 bits
1 (TO0)
Timer clock select register 0 (TCL0)
16-bit timer mode control register (TMC0)
Capture/compare control register 0 (CRC0)
16-bit timer output control register (TOC0)
Port mode register 3 (PM3)
External interrupt mode register 0 (INTM0)
Sampling clock select register (SCS)
MCS = 0
MCS = 1
TI00 input edge cycle
16
2
1/f
X
—
(13.1 ms)
17
2
1/f
1/f
X
X
(26.2 ms)
(200 ns)
18
2
1/f
2
1/f
X
(52.4 ms)
(400 ns)
19
2
2
1/f
2
1/f
X
(104.9 ms)
(800 ns)
Watch timer output edge cycle
= 5.0 MHz
X
Configuration
2 (CR00, CR01)
Note
Resolution
MCS = 0
1/f
X
(200 ns)
2
1/f
X
(400 ns)
2
2
1/f
X
X
(800 ns)
3
2
1/f
X
X
(1.6 s)
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