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23.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V
to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode
in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT
mode immediately after execution of the STOP instruction. After the wait set using the
oscillation stabilization time select register (OSTS), the operating mode is set.
The operating status in the STOP mode is described below.
Setting of STOP Mode
Item
Clock generator
CPU
Port (output latch)
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
A/D converter
D/A converter
Real-time output port
Serial interface
Other than
automatic
transmit/receive
function and
UART
Automatic
transmit/receive
function and
UART
External interrupt
INTP0
INTP1 to INTP6
Bus line for
AD0 to AD7
external
A0 to A15
expansion
ASTB
WR, RD
WAIT
520
CHAPTER 23 STANDBY FUNCTION
Table 23-3. STOP Mode Operating Status
With Subsystem Clock
Only main system clock stops oscillation.
Operation stops.
Status before STOP mode setting is held.
Operable when watch timer output is
selected as count clock (f
XT
count clock of watch timer)
Operable when TI1 and TI2 are selected for the count clock.
Operable when f
is selected for the
XT
count clock.
Operation stops.
Operable.
Operable when external trigger is used or TI1 and TI2 are selected for the 8-bit
timer/event counter count clock.
Operable when externally supplied clock is specified as the serial clock.
Operation stops.
Not operable.
Operable.
High impedance.
Status before STOP mode setting is held.
Low level.
High level.
High impedance.
Without Subsystem Clock
Operation stops.
is selected as
Operation stops.
via a pull-up resistor
DD
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