Interrupt Request Acknowledge Processing Algorithm - NEC PD78056F User Manual

Pd78058f series; pd78058fy series 8-bit single-chip microcontrollers
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Figure 21-13. Interrupt Request Acknowledge Processing Algorithm
Interrupt request
reserve
Yes
the simultaneously generated
XXPR=0 interrupt request have a
Interrupt request
reserve
No
Interrupt request
reserve
Vectored interrupt
servicing
XXIF : Interrupt Request Flag
XXMK : Interrupt Mask Flag
XXPR : Priority Order Specification Flag
IE
: Flag which controls reception of maskable interrupt requests (1 = permitted, 0 = prohibited)
ISP
: Flag which shows the priority order of the interrupt currently being processed (0 = high priority order
interrupt being processed, 1 = no interrupt request being received, or low priority order interrupt being
processed.)
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
Yes (High priority)
Does one of
high priority?
No
IE=1?
Yes
Start
No
IF=1?
Yes (Interrupt Request
Generation)
No
MK=0?
Yes
PR=0?
No (Low Priority)
Any
Simultaneously
Yes
generated
PR=0
interrupt requests?
No
Any
Simultaneously
Yes
generated high-priority
interrupt requests?
No
No
IE=1?
Yes
No
ISP=1?
Yes
Vectored interrupt
servicing
Interrupt request
reserve
Interrupt request
reserve
Interrupt request
reserve
Interrupt request
reserve
495

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