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Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1)
Master Device Processing (Transmitter)
Program Processing
Hardware Operation
Transfer Line
SCK0 Pin
SB0 (SB1) Pin
Slave Device Processing (Receiver)
Program Processing
Hardware Operation
Write
CMDT
RELT
CMDT
Set
Set
Set
to SIO0
1
2
3
A7
A6
CMDD
CMDD
CMDD
Set
Clear
Set
RELD
Set
Serial Transmission
4
5
6
7
8
A5
A4
A3
A2
A1
A0
Address
Serial Reception
Interrupt Servicing
(Preparation for the Next Serial Transfer)
INTCSI0
ACKD
Generation
Set
9
ACK
BUSY
ACKT
WUP 0
Set
INTCSI0
ACK
BUSY
Generation
Output
Output
(When SVA = SIO0)
SCK0
Stop
READY
BUSY
Clear
BUSY
Clear
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