Multiple Interrupt Example - NEC PD78056F User Manual

Pd78058f series; pd78058fy series 8-bit single-chip microcontrollers

Table of Contents

Example 1 Example of multiple interrupt requests being generated twice.

Main Processing

During processing of interrupt INTxx, 2 interrupt requests, INTyy and INTzz, are received and multiple

interrupts are generated. Before reception of each interrupt request, the IE command must be issued

and the interrupt request reception permitted status must exist.

Example 2 Example of multiple interrupts not being generated due to priority order control

During processing of interrupt INTxx, interrupt request INTyy was generated, but the priority order

of this interrupt was lower than that of INTxx, so it was not received and multiple interrupts were not

generated. Interrupt request INTyy was held and received after 1 main processing command was

PR = 0 : High Priority Order Level

PR = 1 : Low Priority Order Level

IE = 0 : Interrupt Request Reception Prohibited

CHAPTER 21 INTERRUPT AND TEST FUNCTIONS

Figure 21-16. Multiple Interrupt Example (1/2)

Main Processing

1 Instruction