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27.2 Operation List
Instruction
Mnemonic
Group
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
MOV
A, [DE]
8-bit data
[DE], A
transfer
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
A, saddr
A, sfr
A, !addr16
XCH
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remarks 1. One instruction clock is the length of 1 clock cycle of the CPU clock (f
clock control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
552
CHAPTER 27 INSTRUCTION SET
Clock
Operands
Byte
Note 1
2
4
3
6
3
–
Note 3
1
2
Note 3
1
2
2
4
2
4
2
–
2
–
3
8
3
8
3
–
2
–
2
–
1
4
1
4
1
4
1
4
2
8
2
8
1
6
1
6
1
6
1
6
Note 3
1
2
2
4
2
–
3
8
10 + n + m
1
4
1
4
2
8
10 + n + m
2
8
10 + n + m
2
8
10 + n + m
Operation
Note 2
–
r
byte
7
(saddr)
byte
7
sfr
byte
–
A
r
–
r
A
5
A
(saddr)
5
(saddr)
A
5
A
sfr
5
sfr
A
9 + n
A
(addr16)
9 + m
(addr16)
A
7
PSW
byte
5
A
PSW
5
PSW
A
5 + n
A
(DE)
5 + m
(DE)
A
5 + n
A
(HL)
5 + m
(HL)
A
9 + n
A
(HL + byte)
9 + m
(HL + byte)
A
7 + n
A
(HL + B)
7 + m
(HL + B)
A
7 + n
A
(HL + C)
7 + m
(HL + C)
A
–
A
r
6
A
(saddr)
6
A
sfr
A
(addr16)
A
(DE)
6 + n + m
A
(HL)
6 + n + m
A
(HL + byte)
A
(HL + B)
A
(HL + C)
Flag
Z AC CY
) selected by the processor
CPU
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