Wait Signal - NEC PD78056F User Manual

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES)
(f) Wait signal (WAIT)
The wait signal is output by a slave device to inform the master device that the slave device is in wait
state due to preparing for transmitting or receiving data.
During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to
delay subsequent transfers. When the wait state is released, the master device can start the next trans-
fer. For the releasing operation of slave devices, see section 17.4.5, "Cautions on Use of I
Mode."
SCL of
6
Master Device
SCL of
Slave Device
SCL
D2
SDA0(SDA1)
SCL of
6 7
Master Device
SCL of
Slave Device
SCL
D2
SDA0(SDA1)
Figure 17-20. Wait Signal
(a) Wait of 8 Clock Cycles
Set low because slave device drives low,
though master device returns to Hi-Z state.
7 8 9
D1 D0
ACK
(b) Wait of 9 Clock Cycles
8 9
D1 D0 ACK
Output based on the value set in ACKE in advance
No wait is inserted after 9th clock cycle.
(and before master device starts next transfer.)
1 2 3
D7 D6 D5
Output by manipulating ACKT
Set low because slave device drives low,
though master device returns to Hi-Z state.
1 2
D7 D6
2
C Bus
4
D4
3
D5
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