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(d) Clear upon RESET input
The HALT mode is cleared upon RESET signal input. As is the case with normal reset operation, a program
is executed after branching to the reset vector address.
Figure 23-3. HALT Mode Release by RESET Input
HALT
Instruction
RESET
Signal
Operating
Mode
Clock
Remarks 1. f
: main system clock oscillation frequency
X
2. ( ): f
: 5.0 MHz
X
Table 23-2. Operation After HALT Mode Release
Release Source
MK
Maskable interrupt
request
Non-maskable interrupt
request
Test input
RESET input
Remark
x: Don't care
CHAPTER 23 STANDBY FUNCTION
Reset
HALT Mode
Period
Oscillation
Oscillation
Stop
PR
IE
0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
–
–
0
–
1
–
–
–
Wait
17
(2
/f
: 26.2 ms)
x
Oscillation
Stabilization
Operating
Wait Status
Mode
Oscillation
ISP
Operation
Next address instruction execution
Interrupt service execution
1
Next address instruction execution
0
1
Interrupt service execution
HALT mode hold
Interrupt service execution
Next address instruction execution
HALT mode hold
Reset processing
519
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