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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES)
Table 17-3. Serial Interface Channel 0 Interrupt Request Signal Generation
Serial Transfer mode
3-wire or 2-wire serial I/O
mode
2
I
C bus mode (transmit)
2
I
C bus mode (receive)
BSYE: Bit 7 of serial bus interface control register (SBIC)
ACKE: Bit 5 of serial bus interface control register (SBIC)
344
BSYE WUP WAT1 WAT0 ACKE
0
0
0
0
0
Other than above
0
0
1
0
0
1
1
0
Other than above
1
0
1
0
0
1
1
0/1
1
1
1
1
1
Other than above
Description
An interrupt request signal is generated each
time 8 serial clocks are counted.
Setting prohibited
An interrupt request signal is generated each
time 8 serial clocks are counted (8-clock wait).
Normally, during transmission the settings WAT21,
WAT0 = 1, 0, are not used. They are used only
when wanting to coordinate receive time and
processing systematically using software. ACK
information is generated by the receiving side,
thus ACKE should be set to 0 (disable).
An interrupt request signal is generated each
time 9 serial clocks are counted (9-clock wait).
ACK information is generated by the receiving
side, thus ACKE should be set to 0 (disable).
Setting prohibited
An interrupt request signal is generated each
time 8 serial clocks are counted (8-clock wait).
ACK information is output by manipulating
ACKT by software after an interrupt request is
generated.
An interrupt request signal is generated each
time 9 serial clocks are counted (9-clock wait).
To automatically generate ACK information,
preset ACKE to 1 before transfer start. However,
in the case of the master, set ACKE to 0
(disable) before receiving the last data.
After address is received, if the values of the
serial I/O shift register 0 (SI00) and the slave
address register (SVA) match, and if the stop
condition is detected, an interrupt request signal
is generated.
To automatically generate ACK information,
preset ACKE to 1 (enable) before transfer start.
Setting prohibited
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