Pci Express Gen 2 Settings Submenu - Congatec conga-IA3 User Manual

8.4.18

PCI Express GEN 2 Settings Submenu

Feature
PCI Express GEN2 Device Register Settings
Completion Timeout
ARI Forwarding
AtomicOp Requester
Enable
AtomicOp Egress Blocking
IDO Request Enable
IDO Completion Enable
LTR Mechanism Enable
End-End TLP Prefix
Blocking
PCI Express GEN2 Link Register Settings
Target Link Speed
Clock Power Management
Compliance SOS
Hardware Autonomous
Width
Hardware Autonomous
Speed
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Options Description
Default In device Functions that support Completion Timeout programmability, allows system software to modify the Completion
Shorter Timeout value. 'Default' 50us to 50ms. If 'Shorter' is selected, software will use shorter timeout ranges supported by
Longer hardware. If 'Longer' is selected, software will use longer timeout ranges.
Disable
Disabled If supported by hardware and set to 'Enabled', the Downstream Port disables its traditional Device Number field being
Enabled 0 enforcement when turning a Type1 Configuration Request into a Type0 Configuration Request, permitting access to
Extended Functions in an ARI Device immediately below the Port. Default value: Disabled
Disabled If supported by hardware and set to 'Enabled', this function initiates AtomicOp Requests only if Bus Master Enable bit is
Enabled in the Command Register Set.
Disabled If supported by hardware and set to 'Enabled', outbound AtomicOp Requests via Egress Ports will be blocked.
Enabled
Disabled
If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit
Enabled (Attribute[2]) requests to be initiated.
Disabled If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit
Enabled (Attribute[2]) requests to be initiated.
Disabled If supported by hardware and set to 'Enabled', this enables the Latency Tolerance Reporting (LTR) Mechanism.
Enabled
Disabled If supported by hardware and set to 'Force to 2.5 GT/s' for Downstream Ports, this sets an upper limit on Link operational
Enabled speed by restricting the values advertised by the Upstream component in its training sequences. When 'Auto' is selected
HW initialized data will be used.
Auto If supported by hardware and set to 'Force to 2.5 GT/s' for Downstream Ports, this sets an upper limit on Link operational
Force to 2.5 GT/s speed by restricting the values advertised by the Upstream component in its training sequences. When 'Auto' is selected
Force to 5.0 GT/s HW initialized data will be used.
Disabled If supported by hardware and set to 'Enabled', the device is permitted to use CLKREQ# signal for power management of
Enabled Link clock in accordance to protocol defined in appropriate form factor specification.
Disabled If supported by hardware and set to 'Enabled', this will force LTSSM to send SKP Ordered Sets between sequences when
Enabled sending Compliance Pattern or Modified Compliance Pattern.
Disabled If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link width except width
Enabled size reduction for the purpose of correcting unstable link operation.
Disabled
If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link speed except speed
Enabled rate reduction for the purpose of correcting unstable link operation.
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