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CPU
2ilog
CPU
The state of the WAIT- input is sampled in the middle of the
second
clock
cycle
by
the falling edge of the CLOCK.
If
WAIT- is low, an additional clock period is added between T2
and
T3.
WAIT-
is sampled again in the middle of this wait
cycle, and additional wait states can be inserted. In
addi-
tion, the CPU board has hardware (T3 WAIT) that allows WAIT-
to be sampled at the falling edge of the T3 clock cycle
and
extends the read/write cycle an extra clock period.
Control
outputs do not change during wait states.
Although
main
memory
is
double
word
organized,
it
is
addressed
as
bytes.
All
instructions
are word aligned,
using even addresses.
Within a In-bit word, the most signi-
ficant
byte
(D8-DlS) is addressed by the low order address
(AD
=
Low), and the least significant
byte
(DO
07)
is
addressed by the high-order address (AD
=
High) •.
6.3.
Input/Output Timing
I/O timing is
similar
to
the
memory
read/write
timing,
except that one wait state is automatically inserted between
T2 and T3.
A 280 peripheral handshaking control translation
circuit
causes
the
Z800lA CPU to emulate the Z80B control
signals IORQ-, Ml-, RD-, and RETI.
Four different operations are performed between the CPU
and
its peripherals:
1.
CPU writing into the peripheral device.
2.
CPU reading from the peripheral device.
3.
Peripheral interrupting the CPU, which responds with an
Interrupt Ac knowl edg e •
4.
CPU simulating a Return from Interrupt (RETI) signal.
The first two operations - writing or reading from the peri-
pheral
are
fairly straight forward.
Two three-to-eight
LS138 decoders, enabled by the
decoded
status
signal
I/O
REF-,
decodes
the
latched I/O addresses and generates CE-
signals to the CTC 0-2, SIO 0-3, and
PIO
individual
peri-
pheral
devices.
The
ZaOOlA
uses the full l6-bit address
space for I/O. All" ports require an odd address to interface
with the data
bus
(lower byte).
Writing to the enabled peripheral is performed when IORQ- is
low
while
RD- is high.
A read operation is performed when
IORQ- is low while RD- is low.
5-3
2ilog
6-3
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