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CPU
Zilog
CPU
segment
trap request outputs a one on the Address/Data line
associated with the number in its ID field. An MMU that
has
not
generated
a segment trap outputs a zero on its associ-
ated A/D line.
Following the
acknowledge
cycle,
the
CPU
automatically
pushes
the
program status words and program
counter onto the system
stack,
and
loads
a
new .program
status
word
and
program
counter
from the program status
area. The SEGMENT TRAP (SEGT-) line is reset during the seg-
ment trap acknowledge cycle, and no SUP- signal is generated
during the stack push.
The CPU board provides hardware which generates SEGMENT TRAP
(SEGT-)
and
SUP-
signals when an access is made to system
segments (O, 1, 64, 65) in normal mode.
The
violation
is
detected
by
U3,
Ul?
and
U23
(sheet 10).
Flip-flop U20
(sheet 8) generates SEGT-
signal
upon
a
violation.
The
SEGT-
line
is
reset
when
segment
trap
is acknowledged
(SEGTACK- goes high).
Similarily, the
other
half
of
U20
generates the SUP- signal.
4-21
Zilog
4-21
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