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CPU
00377
Zilog
CPU
..... 8 - - - -.....- - -.....ausIE02 P1-8a
Figure
4-6
Interrupt priority Connection (Sheet
14)
4.5.3.
NMI Identification:
On recelvlng an
NMI,
the
CPU
responds by generating an NMI Acknowledge transaction status
code
0101
orrthe-ZBI status- lines (53-SO). The
CPU
status
decoding logic (U25,U2n) then produces an NMI logic enabling
signal at the AND gate (US). If the source
of
the
NMI
is
from
the
CPU
board,
the
NMI logic hardware on the board
enables a four-bit error buffer, the NMI Identifier Register
(U12) •
The NMI identifier register encodes the first four data bits
(ADO-AD3)
of
the
ADO-ADIS internal address data bus as an
NMI Identifier word. The CPU identifies the
source
of
the
NMI
by
reading
the
four
data bits (ADO-AD3) of a 16-bit
identifier word placed on the address/data bus.
This NMI identifier word is coded as a Manual,
Power
Fail,
or
ECC
Error as
shown in Table 3-3.
If the NMI source is
not one of the three listed and is external to
the
proces-
sor,
the NMI identifier register is not enabled and the 16-
bit identifier word is read from the system bus.
4.5.4.
SyS1;E!Wi
.Re~et.
Logic
(SJ1eet
11):
The
system
reset
logic
is initIated by the front panel RESET pushbutton sig-
'nal SW RESET- at P2-27.
This signal is buffered and applied
to the negative OR gate U78 (Figure 4-7).
4-9 .
Zi10g
4-9
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