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CPU
Zilog
CPU
4.4.1.
SIO/CPU Interface:
The SIO devices communicate with
the Z800IA CPU over the internal data bus using data bits DO
through D7.
SID options are controlled by software and
set
when
control
bytes
are
written
from
the CPU to the SIO
registers.
The options are established separately for
each
SIO channel of the four SIO devices.
Once this initial step
is complete, the remaining communication between the SIO and
the
CPU
is by vectored interrupt.
The SIO informs the CPU
by
the
interrupt
that
a
single
character
transfer
is
required.
The
CPU
responds
by branching to an interrupt
service routine for
the
single
character
transfer.
The
memory
address for beginning the service routine is derived
from the interrupt vector supplied by the SID. Each
channel
of each SIO is assigned a unique vector.
4.5.
Interrupts
When an interrupt or trap is
det~cted
by the Z8001A CPU, the
subsequent
instruction
fetch
1S
initialized but aborted.
The next CPU machine cycle is an interrupt acknowledge tran-
saction.
The transaction acknowledges an interrupt or trap
and reads a 16-bit identifier word
from
the
device
that
generated
the
interrupt.
The identifier word is stored by
the CPU in System stack along with program
status
informa-
tion
and either encoded for a vectored (VI) or non-maskable
interrupt (NMI) and output on ZBI status lines SO through S4
and
also
to
the
CPU
Status Decode logic.
A nonvectored
interrupt is available on the
ZBI,
but
it
is
unused
on
present board products.
4.5.1.
vectored Interrupt:
For a vectored interrupt, tran-
saction
code
0111
is
placed on the external hardware CPU
Status Decode logic.
Transaction code 0111 is presented
at
A,B,C,
and
G2A of the CPU Status Decode logic U25 and U26.
A VI ACK signal is decoded and" combined with the
peripheral
handshaking
logic to produce the Ml-, RD-, and IORQ- inputs
on the Z80B device
acknowledging
the
vectored
interrupt.
The
device
then places the 8-bit vector on the data bus to
be read by the CPU.
The CPU reads the 16-bit
word
(vector
and
8-bit status byte) and it is stored on the system stack
of the CPU.
New status information is loaded into the
pro-
gram counter(PC) and the flag control word (FCW).
4-7
Zilog
4-7
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