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CPU
2ilog
CPU
similarly to other types of interrupts.
3.5.2.
System Confi9uration:
The system configuration
for
the System 8000 CPU is by choice of bit D2 (SEG USER)
in the
system configuration reg ister for
ei ther
a
O.
(low)
non-
segmented
user
program
or a 1 (high) for a segmented user
program.
The operating system is
presently
configured
by
jumpering of the board memory management control logic for a
non-segmented operating system.
The
present
configuration
options are as follows:
Operating system
S8
=
0,
SEG USER bit D2
8U
=
a
Operating system
S8
=
0,
SEG USER bit D2
SU
=
1
3.5.2.1
SS=O,SU=O:
This configuration is used
for
a
non-
segmented
operating
system running non-segmented user pro-
grams.
The operating system runs in segment
a
while a
user
program
runs
in
any
segment
2
through 63 , with 63 the
recommended segment.
The MMU
Ml
is
enabled
for
program
references
indicated by a CPU status code llxx, an instruc-
tion space access.
For memory references other
than
program
references,
the
address
offset generated by the CPU is compared against the
contents of the SBR if the segment number is zero or one, or
with
the
NBR
if
the
segment
number is 2 to 63.
If the
result is less than zero, the select logic enables the
data
MMU
(M2),
otherwise the stack MMU M3 is enabled.
Hardware
on the board detects CPU Normal
Mode
reference
to
System
Mode
segment
0,
generates a segment trap violation to the
CPU and disables the MMUs.
3.5.2.2
55=0, SU=1:
When the 8CR SEG USER bit
D2
is
a
1
(high), the configuration supports a non-segmented operating
system running a segmented user process.
When the CPU is in
the
system
mode
with
the segment number zero or one, the
operation is the same as above.
The code,
data
and
stack
references
are directed to MI,M2, and M3, respectively, and
the contents of the SBR are used to select between data
and
stack
references.
In
normal
mode, MMU M2 is enabled for
segment numbers 2 through 63, and MMUM3 is enabled for -seg-
ment numbers 66 through 127.
If a memory reference is made to segment 0,
1,
64,
or
65
while the CPU is in normal mode, a segment trap violation is
generated and all
three
MMUs
are
disabled.
A
suppress
3-17
2ilog
3-17
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