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CPU
1
2
Zi10g
3
4
CPU
00188
Figure 4-9
Setting Console Baud Rate (Table 2-9)
(96QO Baud) for a-inch Disk (Sheet 14)
4.9.1.
SCR Configuration:
The lower data bits
DO
through
D3
are read/write and enable the system configuration func-
tions.
All bits in the lower nibble are cleared
on
system
reset
to
initialize
the
system.
The Dl (MMU-ONH) and D2
(SEG USER) bits enable the MMUs
and
select
segmented
and
non-segmented
user
respectively.
The
DO
(BDMEMON-) bit
enables the onboard memory function at system
reset
(logic
0)
and main memory on logic
1.
On system reset, the
01
bit
disables the three MMUs (logic 0) and all references to main
memory
are
transmitted
as
logical
addresses.
Writing a
logic 1 to the Dl bit enables all
three
MHUs
for
address
translation
and
all
main
memory
references
are
mapped
through the MMUs.
Bit D3 (CLR PARITY-) enables or
disables
the
NMI
derived
from
a parity error or a non-correctable
double bit error from the ECC Controller.
4.9.2.
Segmented/Non-segmented User:
The operating
system
software
configures
the system configuration register(SCR)
for segmented/non-segmented user.
The
SCR
register
(U3~)
outputs
the
configuration
bit
02
(SEG USER) to enable the
segmented user function.
The D2 bit is cleared at RESET
to
a
logic 0, for non-segmented user, and must be set to logic
1
(SEG USER) before the operating system can support a
seg-
mented user.
When the
SCR
D2 (SEG USER) bit is logic
0,
the user
process
can
occupy
anyone of the segments 2 through 63.
The user
code references are routed through the MHU Ml'.
Data
refer-
ences
are
routed through the data MMU M2 if address offset
is less than the normal break register and to the status MMU
M3
if address offset is equal to or greatet than the normal
4-16
Zilog
4-16
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