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CPU
Zilog
CPU
with the program status information, is stored on the system
stack and new information is loaded into the PC and FCW.
The CPU generates an
NMI
acknowledge
status
code
"0101"
(ST3-STO)
when
the
NMI
source
is one of those listed in
Table 3-3. The external hardware
on
the
System
8000
CPU
enables
a
four
bit
error buffer to place on address/data
lines ADO through AD3 a 4-bit NMI
identifier
coded
as
in
Table 3-3.
Table 3-3.
NMI Identification
NMI SOURCE
MANUAL
POWER FAIL
ECC ERROR
AD3
o
o
o
AD2
o
o
1
AD1
o
1
o
ADO
1
o
o
Bits AD4 through AD15 are "don't care" bits in an
NMI
ack-
nowledge
identifier
word
if
the NMI source is one of the
above.
If the NMI source is external to the
processor
and
not
listed
above,
the
NMI error buffer remains off and a
16-bit identifier word is read from the system bus.
3.4.4.
Vectored Interrupts:
The 16-bit identifier word can
be
used to identify the source of an interrupt or trap.
In
a vectored interrupt(VI), the identifier is also used by the
CPU
as a
pointer.
The pointer selects a particular service
routine
as~ociated
with the source of the interrupt.
3.4.5.
The VI Daisy Chain:
The Z80B SIO, Z80B CTC and Z80B
PIO
are all Z-BUS peripherals designed to interface readily
with the Zilog Z80 cPU.
Special logic has been
implemented
on the System 8000 CPU board to mimic the Z80 CPU timing and
the Z80 peripherals cannot discern that the
Z8001A
CPU
is
the host processor.
Because of the large number of Z80 peripherals on the System
8000 CPU, an interrupt daisy chain assigns priority to these
devices to hasten the interrupt
request
time.
Basically,
each Z80 device on 'the prOcessor contains two lines (IEI and
lEO) which serve as links in the daisy
chain.
Figure
3-1
shows the interrupt daisy chain for the System 8000 CPU.
lEI : Interrupt Enable In
(Input, active high)
3-11
Zil09
3-11
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