Peripheral Handshaking Logic; T3 Wait State Generator Logic - ZiLOG System 8000 Hardware Reference Manual

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Figure 4-10 T3 Wait State Generator Logic (Sheet 11)
4.10.4. peripheral Handshaking Logic: The Z80S Peripherals
(PIO,SIOs,and CTCs) require the peripheral handshaking logic
(Figure 4-10) for the Z8001A CPU to emulate the Z80S control
signals IORQ-,Ml-, and RD-. The two L8138 decoders (U24,
U39,sheet12) are enabled by the decoded status signal I/O
REF and decode the latched I/O address while generating chip
enable (CE-) signals to the individual peripheral devices.
A write operation into the enabled peripheral is performed
when IORQ- is low while RD- is high. A read operation is
pertormed when both IORQ- and RD- are low. The peripheral
interrupt of the CPU is by a vectored interrupt (VI) pulling
the VI- input of the CPU low. The CPU samples this input at
a specified time prior to the end of any instruction. The
Z8001A CPU then acknowledges the interrupt·with the specific
status code (VIACK-) from the status logic (U25,sheet 3) •
The VIACK- signal is input at U41 and makes IORQ- active
during an Ml- (normally opcode fetch) cycle indicating a
vectored interrupt acknowledge to the peripheral.
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