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CPU
Zilog
CPU
2.6.1.
ZBI Signal Definitions:
The ZBI signal
definitions
are
listed
in
the
System
8000 Hardware Reference Manual
(03-3198-01) (Para.4.4)
2.6.2.
ZBI Status Lines:
The Z8001A CPU outputs the status
(8TO-ST3)
codes
that when active high indicate the type of
transaction currently on the ZBI bus.
The S4 code
is
gen-
erated
by board hardware.
The encoding of these signals is
shown in Table 2-7.
Table 2-7.
Status Transaction Coding
84
a
o
o
o
o
o
o
o
o
o
o
a
o
o
o
o
1
S3
o
o
o
o
o
o
o
o
1
1
1
1
1
1
1
1
x
S2
o
a
o
a
1
1
1
1
a
o
a
o
1
1
1
1
x
81
o
o
1
1
o
o
1
1
o
o
1
1
o
o
1
1
x
So
o
1
o
1
o
1
o
1
a
1
o
1
o
1
o
1
x
TRANSACTION
Internal Operation
Memory refresh
I/O reference
Special I/O reference
Segment trap acknowledge
INT 1 Interrupt Acknowledge
INT 3 Interrupt Acknowledge
INT 2 Interrupt Acknowledge
Data Memory Request
Stack memory request
Transfer between data memory
and EPU
Transfer between stack memory
and EPU
program reference, nth cycle
program reference, 1st cycle
Transfer between CPU and EPU
Reserved
Reserved
2.6.3.
Data Width Codes:
The Byte-Word Select
(B/W-)
and
Word/Long-word
Select (W/LW-) signals are encoded to define
the data access width as shown in Table 2-8.
2-e:;
Zi10g
2-0
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