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CPU
Zilog
CPU
Configuration
1
Supports
a
non-segmented
ZEUS
operating
system.
In this mode, the operating system
is expected to run in logical segments 0
and
1
while
User
processes
can
be
either
segmented
or
non-
segmented.
Non-segmented user processes can run in any
logical
segment from 2 through 63 while
~egmented
User
processes can run in one or
more
logical
segments
2
through
63 or 66 through 127.
The ZEUS operating sys-
tem must configure the
hardware
correctly
before
it
begins
to
run the corresponding type of User process.
This is done by setting the SEG-USER bit of the SCR.
Configuration 2 - Supports a segmented
operating
sys-
tem.
In this mode, the operating system runs segmented
and resides in all logical segments from 0 through
63.
Non-segmented
and
segmented user.processes have their
own set of
segments.
Segmented
User
processes
can
reside
in any of the segments from 0 through 127 while
non-segmented User processes are
still
restricted
to
segments 2 through 63.
3.5.1.
MHU Configuration and Control:
3.5.1.1
Non-segmented Operating System:
The
non-segmented
operating
system runs in segment 0 using Segment Descriptor
Register (SDR) 0 of the MMUs M1,M2, and
M3
for
respective
code, data, and stack areas.
MMU Ml is used for translating
program memory references while
M2
and
M3
are
used
for
translating all other memory references.
The selection between M2 and M3 is
based
on
a
comparison
between
the
logical address and the contents of the System
Break Register (SBR), a program addressable hardware
regis-
ter.
Logical
addresses with values lower than the SBR are
treated as data addresses and are directed to the
Data
MMU
(M2) •
Logical
addresses that are equal to or greater than
the SBR are treated as stack addresses and are
directed
to
the Stack MMU (M3).
3.5.1.2
Non-segmented User program:
A
non-segmented
User
program
runs
in segment 63.
However, the hardware permits
any segment between 2 and 63 to be used.
As in the case
of
the non-segmented operating. system, the SDR in segment 63 in
MI, M2, and M3 is used for separate code,
data,
and
stack
areas,
respectively.
However,
the
normal break register
(NBR) is used instead of
the
SBR
to
distinguish
between
data,
and
stack
references.
The
NBR
is also a program
addressable hardware register.
3-15
Zilog
3-15
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