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CPU
Zilog
CPU
The highest order peripheral has its
IEI
permanently
tied
high.
For
any peripheral that has no interrupt pending or
under service, IEO
=
lEI.
Any peripheral that has an inter-
rupt pending or under service forces its IEO low.
To ensure stable conditions in the daisy-chain,. all
inter-
rupt status sigDals are prevented from changing while Ml- is
low.
When IORQ- is
low,
the
highest
priority
interrupt
requestor (lEI High) places its interrupt vector on the data
bus and sets its internal interrupt-under-service latch.
i1 , ' - -
....J1
\~
__."I
RD
1£1 :::.::..:
: . / - - - - - - ' \ . : : : __
::~
DATA
---------....c(
VECTOR
)>----
Figure 6-6 . Interrupt Acknowledge Cycle
6.5.1.
Return from Interrupt:
At the end of
an
interrupt
service
routine, the interrupt- under- service latch in the
peripheral must be reset.
The normal daisy-chain
operation
can
be
used
to detect an impending interrupt, however,
it
can not distinquish beween an interrupt under service and
a
pending
unacknowledged
interrupt
of
a
higher. priority.
Whenever EO is decoded, the daisy-chain is modified by forc-
ing high the lEO of any interrupt that has not yet been ack-
nowledged.
Thus,
the
daisy-chain
identifies
the
device
presently under service as the only one with an lEI high and
a lEO low.
If the next opcode byte is
40,
the
interrupt-
under-service latch is reset (Figure
6-7).
The ZaODIA CPU emulates the instruction by a combination
of
hardware
and
software.
A software sequence at the end of
everyi.nterrupf service routine writes two consecutive bytes
(EO
and 40), to a hardware FFEI address which simulates the
RETI.
.
6-7
Zilog
6-7
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