Byte Swap Buffer; Memory Management Control Logic - ZiLOG System 8000 Hardware Reference Manual

CPU Zilog
CPU
low the high byte is read or written, when high the low byte
is read or written.
For word operations for both read and write, the B/W- CPU
output is low and the select logic enables both banks of
memory.
4.7. Byte Swap Buffer
The byte swap buffer (Ul12, sheet 13) is an LS244 octal
three state buffer activated on an offboard byte read of an
even address by a special byte swap control logic circuit.
On an even address (ADO low) the least significant data byte
(ADO-AD7) on the ZBI bus is placed on the most significant
half (IAD8- IAD15) of the CPU address/data bus when the byte
swap buffer is enabled.
The signal ENA BYTE SWAP and the inverted ENA BYTE SWAP- are
created by control logic (sheet 4) to enable the the byte
swap buffer (Ul12) and disable the bidirectional buffers
(Ulll,Ul13, sheet 13). The input signals IR/W-, IB/W-, pnd
latched address bit LAD
a
are AND gated (U33), when high, to
create the input buffer enable signal (E~A BYTE SWAP) and
the inverted ENA BYTE SWAP- signal.
The ENA BYTE SWAP and NON BD signals are gated at U31 with
the gated output of the IW/R- and IDS- signals from the bus
address/data steering logic to enable the byte swap buffer.
The inverted ENA BYTE SWAP- and NON BD signals are gated at
the same time to disable the buffers Ulll and Ul13.
The low byte (ADO-AD7) input of the ZBI bus, normally on
the bidirectional buffer (UIII), is placed by the byte swap
buffer{UI12) from the ZBI to the upper half of the CPU data
bus (IAD8-IAD15).
4.8. Memory Management Control Logic
The three Zilog Z80l0A memory management units (U8o,U87,and
USS) each having 64 separate segment descriptor registers
that accept a 23-bit logical memory segment address to be
translated into a 24-bit physical memory location.
Logic on the board partitions segments into system segments
(0,1, 64, and 65) and user segments (logical segments 2-63,
00-127). A reference to a system segment always enables a
system break register. A reference to user segment always
enables the normal break register. Normal mode references to
system segments are not allowed and result in a segment
4-12
Zilog 4-12