Interrupt Operation; Write Cycle; Read Cycle - ZiLOG System 8000 Hardware Reference Manual

CPU
Zilog CPU
T1 T2
TW
T3
T 1
III
Ci
CHANNEL ADDRESS
IORO
RO
M1
DATA
X
IN
X
Figur-e
6-2
Write Cycle
T1 T2
TW T3
T 1
' 1 1
CE
CHANNEL ADDRESS
iffiiQ
iii
ii
( )
DATA
OUT
Figure
6-3
Read Cycle
6.4. Interrupt Operation
The ZaOOI CPU recognizes the vectored, non-maskable, and
segment trap interrupt inputs which are sampled at the
beginning of T3 in the last machine cycle of any instruc-
tion. In response to the inte~rupt or trap, the subsequent
status output instruction fetch cycle is exercised but
aborted. The next machine cycle is the interrupt or segment
trap acknowledge cycle. This cycle has five automatic wait
states, with additional wait states possible. After the
last wait state, The CPU reads the information on ADO - ADlS
which identifies the source of the interrupt or trap. After
the acknowledge cycle, the N/S output indicates the
automatic change to system mode.
6-4
Zilog 6-4