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CPU
Zilog
CPU
Also applied to U78 is the onboard SOFT RESET-
signal
from
the
program
shutdown in the event of power fail.
The SOFT
RESET- signal is generated by accessing
I/O
address
FFE9.
On
being
OR
gated, either of these two signals enable the
J-K flip-flop (U83) generating a reset.
When the system power supply detects a low
voltage
output,
the POWER FAIL- signal at PI-27A comes from the system power
supply to the K input of US3.
The K input is normally
high
from
pull-up
resistor RIS.
Output
Q-
of US3 is clocked by
an inverted Clock
B
signal to produce the system reset
sig-
nal MRESET-.
The POWER FAIL signal is an inverted output to the NMI logic
and
produces
the
BUS NMI- to the
cpu.
The CPU then reads
the NMI identifier from the address bus and issues
a
reset
to the system
by
performing a soft reset.
PZ-27C......
SW
....
R £SET= .....
---ot--......
-..---t
pt-27Aa-:;~.::.=~F.:;:M.::;'.
_ _
---L
.....
--=-t
.,REIET·
Figure
4-7
System Reset Logic (Sheet
11)
4.6.
Memory
Addressing
The address generated by the ZSOOIA CPU is either a byte
or
word address.
However, the CPU board local memory is organ-
ized
as
I6-bit
words.
All
the
instructions
and
word
operands
are
addressed
by even addresses and for all word
transactions the least significant address data bit (ADO) is
zero.
For all byte transactions to local or main memory, the least
significant address/data bit (ADO), determines that the most
significant data byte is needed when
ADO
is
even
(zero).
The
least
significant byte is needed when address/data bit
(ADO)
is odd (one).
For a data byte read from the
ZSI
bus
of
an even address to meet ZSI specification, the low order
4-10
Zil09
4-10
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