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CPU
Zilog
SECTION 4
CIRCUIT DESCRIPTION
CPU
The
major
elements
of
the
System
8000
CPU
board
are
described
in
this section and each element is explained in
its relation to the system.
The
following
text
describes
the
major circuits and devices involved in the operation of
the System 8000 CPU board.
Reference is made to
the
logic
drawings
included
in
the
Appendix for clarity and under-
stand ing •
4.1.
Z8001A CPU
The 6MHz Z8001A CPU is the host microprocessor of the System
8000.
It is a 48 pin segmented/nonsegmented CPU with 16-bit
programmable accumulator and index
registers
for
byte
or
word
operation.
The
system
and
normal
stack
pointers
separate system from normal program information.
Certain instructions, including all
I/O
instructions,
can
only
be
executed in system mode.
Present configuration of
the System 8000 CPU is as a nonsegmented operating system.
Program status from the status registers is provided to
the
program
counter which consists of two
16~bit
registers con-
taining the program counter offset and 7-bit segment number.
The
flag
and
control
word
(FCW)
consists of two 16-bit
registers
with
flags
for
segmented/nonsegmented,
system/normal, and vectored and nonvectored interrupt opera-
tion.
When an interrrupt
or
trap
occurs,
the
current
program
·status, consisting of the PC, FCW, and 16-bit identifier, is
automatically pushed on the system stack.
The System 8000 CPU communicates with the System 8000 memory
controller
and
peripherals through the Zilog ZBI bus back-
plane. However, I/O and terminal and
printer
communication
is
through the eight full duplex RS232C serial channels and
one parallel printer I/O port supplied by the four
SIO
and
single PIO onboard chips.
Handshaking logic generates Ml-, RD-, and IORQ- signals that
interface the Z80 peripherals and the Z8001A CPU and emulate
the Z80 CPU.
4-1
Zilog
4-1
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