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CPU
Zilog
CPU
Table 3-1.
I/O Address,Device and Channel
I/O
ADDRESS
I/O DEVICE AND CHANNEL
FF81
SIa 0, channel 0, data
FF83
SIa 0, channel 1, data
FF85
SIO 0, channel 0, control
FF87
SIO 0, channel 1, control
FF89
SIO 1, channel 2, data
FF8B
SIO 1, channel 3, data
FF8D
SIa 1, channel 2, control
FF8F
SIO 1, channel 3, control
FF91
SIO 2, channel 4, data
FF93
SIO 2, channel 5, data
FF95
SIO 2, channel 4, control
FF97
SIO 2, channel 5, control
FF99
SIO 3, channel 5, data
FF9B
SIa 3, channel 7, data
FF9D
SIO 3, channel 6, control
FF9F
SIO 3, channel 7, control
FFAI
CTC 0, channel 0, (baud
a
for SIO 0, channel 0)
FFA3
CTC 0, channel 1, (baud 1 for SIa 0, channel 1)
FFA5
CTC 0, channel 2, (baud 2 for SIa 1, channel 2)
FFA7
CTC 0, channel 3
FFA9
CTC 1, channel 0, (baud 3 for SIa 1, channel 3)
FFAB
CTC 1, channel 1, (baud
4
for SIa 2, channel 4)
FFAD
CTC 1, channel 2, (baud 5 for SIO 2, channel 5)
FFAF
CTC 1, channel 3
FFBI
CTC 2, channel 0, (baud
6
for SIO 3, channel 6)
FFB3
CTC 2, channel 1, (baud
7
for SIO 3, channel 7)
FFE5
CTC
2, channel
2
FFB7
eTC 2, channel 3
FFB9
PIO 0, channel A, data
FFBD
PIO 0, channel A, control
FFBB
PIO 0, channel B, data
FFBF
PIO 0, channel B, control
FFCI
SCR, read/write,System Config. Register
FFC9
SBR, read/write,System Break Register
FFDI
NBR, read/write,Normal Break Register
FFD9
SVR, read segment trap segment address
FFE9
Soft Reset
FFFI
Low-Byte Register,read segment trap low-byte address
FFF9
Low-Byte Register,read segment trap IFI low-byte
3-7
Zilog
3-7
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