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CPU
Zilog
CPU
3.3.2.
Special I/O:
The special I/O address space
of
the
Z800lA
CPU
is
used to communicate with one or more of the
three Z8010A MMUs.
Any special I/O
reference
detected
in
the
CPU
status
disables
both
the
onboard
and offboard
address buffers and enables the I/O
registers
internal
to
the MMUs.
The special I/O address. determines
at
which
port
of
the
selected
MMU
the
information
is
either read or written.
Address bit ADO must be low on all MMU references since
the
MMUs
are
addressed
on
even byte boundries.
Address bits
ADI, AD2,and AD3 can individually select the Code, Data, and
Stack
MMUs,
respectively, when low (0).
The same data can
be written to the same input/output port of all
three
MMUs
by
a
special
I/O
Write
with
all three address bits ADI
through AD3 low.
The byte operands are transferred
to
the
MMUs
over
AD8
through
ADl5
of
the
CPU's
internal
address/data bus.
The address bits ADO through AD7 are
not
recognized
by any of the three MMUs.
A summary of the spe-
cial I/O addresses of the Code,
Data,
and
Stack
MMUs
is
given in Table 3-2.
Table 3-2.
Special I/O MHU Address
CODE
OOFC
OIFC
02FC
03FC
04FC
05FC
06FC
07FC
08FC
09FC
OAFC
OBFC
OCFC
ODFC
OEFC
OFFC
IIFC
13FC
14FC
15FC
16FC
20FC
DATA
OOFA
OIFA
02FA
03FA
04FA
05FA
06FA
07FA
08FA
09FA
OAFA
OBFA
OCFA
ODFA
OEFA
OFFA
11FA
13FA
14FA
15FA
16FA
20FA
STACK
OOF6
OlF6
02F6
03Ffi
04F6
05F6
06F6
07F6
08F6
09F6
OAF6
OBF6
OCF6
ODF6
OEF6
OFF6
IlF6
13F6
14F6
15F6
16F6
20F6
DESCRIPTION
Read/write mode register
Read/write segment address register(SAR)
Read violation type register
Read violation segment number register
Read violation offset(high-byte) register
Read bus status register
Read instruction segment number register
Read instruction offset (high-byte) register
Read/write
base field
Read/write limit field
Read/write attribute field
Read/write descriptor,all fields
Read/write base field,increment SAR
Read/write limit field, increment SAR
Read/write attribute field,increment SAR
Read/write descriptor,increment SAR
Reset violation type register
Reset SWW flag in VTR register
Reset Fatal flag in VTR register
Set all CPU inhibit attribute flags
Set all DMA inhibit attribute flags
Read/write descriptor selector counter
3-8
Zilog
3-8
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