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CPU
1.1.
Description
Zilog
SECTION 1
OVERVIEW
CPU
The Zilog System 8000 Central
Processor
Unit
(CPU)
board
(Figure 1-1) is the controlling processor board for the Sys-
tem 8000.
The System 8000 CPU is designed around the Zilog Z8001A
16-
bit microprocessor which uses an advanced instruction set, 8
Mbyte segmented addressing
space,
and
16
bit
registers.
Memory
management increases the addressing capability to 16
Mbyte by dynamic
segment
relocation
and
protection
from
three
Z8010A
Memory
Management
Units and special control
logic.
Software addressing is then independent of the
phy-
sical
memory
address
and
eliminates
the need to specify
where information is actually located in memory.
The Zilog Z8001A segmented
6
MHz
microprocessor
runs
the
Zilog
ZEUS operating system, a high performance implementa-
tion of UNIX.
The
operating
system
presently
implements
non-segmented
operation
while
user programs can be either
segmented or non-segmented.
The System 8000 CPU board initiates
and
controls
transac-
tions
on
both
the system and input/output (I/O) bus.
The
Z8001A
microprocessor acts as the
host
and
controls
the
system bus Z-Bus Backplane Interconnect (ZBI) and all paral-
lel and serial I/O to and from the system.
The CPU board (Figure 1-2), at P2/J21, connects directly
to
and
controls
the
I/O
bus
and
all I/O transactions pass
through P2 to the parallel port or one of eight
serial
I/O
ports.
The eight serial channels support the RS-232C stan-
dard.
The System 8000 CPU board is one of several printed
circuit
boards in a system and is inserted into slot one of the card
cage.
Plug Pl/Jll connects to the ZBI bus and P2/J2l
connects
to
the
I/O
bus.
The
connectors
are three level 96 pin Euro
standard. The Zilog ZBI is
a
32-bit
backplane
bus
which
interconnects
the
boards of the system. Figure 1-1 identi-
fies the components of the System 8000 CPU board.
1-1
Zilog
1-1
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