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CPU
Zilog
CPU
The System 8000 uses
the
16-bit
word
addressing
of
the
Z8001A
CPU
for
byte
addressing
of
local memory and I/O
addressing to the onboard I/O devices.
The CPU board uses a
16-bit
time
shared
data bus latched by the onboard memory
address buffers (U62,U47 LS373
Octal
Transparent
Latches)
and
controlled
by the Address Strobe (AS) signal.
Onboard
memory data buffers (U63,U46) are
bidirectional
bus
tran-
sceivers,
with data direction controlled by the W/R- signal
from inverter (Un8).
A BD
DATA
ENABLE-
signal
is
generated
to
the
onboard
memorY/I/O
data
buffers
(U63,U46) from the onboard enable
data logic which is gated by the IDS,IW/R- and
the
onboard
memory
selector
NON
BD signals.
The CPU has 3-state buf-
fered status and control signal outputs from Ul18
for
off-
board
status and control.
The BUS ACK- signal disables the
CPU status and control bus buffers and notifies ZBI
devices
that the CPU has relinquished the bus.
An indication of bus
release is provided by an LED
on
the
front
edge
of
the
board.
4.2.
Clock Generation
The clocks on the CPU board for System 8000 and
I/O
timing
originate from a 44.4 MHz oscillator (U85).
The divide by 8
(U98)
is used for the 5.5 MHz onboard square wave
clocks
A
and
B.
After
passing
through
a
Z80 driver, Clock A is
applied to the Z8001 CPU and the MMUs.
Clock B
is
applied
to
the
I/O
peripheral
devices
(CTCs,SIOs, and PIO) also
after passing through a Z80 driver.
The separate buffered output bus clock ,B CLK,
synchronizes
all
elements of the system and ZBI bus transfers.
A master
clock (MCLK) output, four times the B
clock
frequency,
is
also derived from U98 and serves as the master clock for the
System 8000.
The clock generation circuit is shown in
Fig-
ure 4-1.
4-2
Zilog
4-2
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