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CPU
Zilog
CPU
The main memory address space begins at location
4000
hex,
and
when
the
local
memory space is enabled, a dead space
exists from locations 2800 through 3FFF hex.
All references
to
local
memory
require
one
wait-state insertion.
Main
memory references require virtually
ho
wait-states.
How-
ever, main memory references that activate the error correc-
tion logic on the ECC controller do require
one
wait-state
insertion.
3.2.3.
Main
Memory:
The
System
8000
CPU
main
memory
address space is 16 Mbytes using the board memory management
units (MMUs). The SCR Dl bit enables the MMUs.
At power-up or system reset, the SCR Dl
bit
(MMU
ONH)
is
cleared (logic 0) and all memory references through the MMUs
are inhibited.
Main memory references are
routed
directly
from
the
Z8001A
CPU
to the main memory over the ZSI bus.
The logical addresses generated by the CPU are the
physical
addresses
received
by
the
main
memory.
Therefore, for
addresses AD23 through ADO:
AD23
=
AD22 - AD16
=
ADIS - ADO
=
o
7-bit segment,by instruction or PC
16-bit offset address,by instruction or PC
Memory Management references to main memory cannot
be
gen-
erated
by
the MMUs until the SCR Dl bit is set to logic 1.
The status of this bit however, does not impair the program-
ming of the three MMUs with special I/O instructions.
Refer
to the SCR and Memory Management sections for more
detailed
description.
3.2.4.
Byte Transactions:
When a byte transaction is being
executed by the Z800IA CPU, the Byte-Word Select line (B/W-)
is high for byte selection.
3.2.4.1
Byte Read: For a local memory read, the
Read/Write
(R/W-)
output
line
is
high
and both banks of memory are
read.
The reading of the required byte
is
on
either
the
upper
or
lower
half
of
the Z800IA CPU address/data bus.
Either the high or the low half of the address/data
bus
is
selected
by
the CPU for the byte destination, depending on
the least significant address
bit
AO
being
even
or
odd
respectively.
When AD is low, the upper (even) half of the
address/data bus is read.
If AO is high,
the
lower
(odd)
half
of
the data bus is read.
During a byte read transac-
tion between the
CPU
and
memory,
the
memory
need
only
3-4
Zilog
3-4
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