Introduction; Mode Registers; Input And Output Registers; Port - ZiLOG Z8 Technical Manual

9.1 INTRODUCTION
The Z8 has 32 lines dedicated to input and out-
put. These lines are grouped into four 8-bit
ports and are configurable as input, output, or
address/data. Under software control, the ports
can be programmed to provide address/data, timing,
status, serial, and parallel input/output with or
without handshake.
All ports have active pull-ups and pull-downs
compatible with TTL loads. In addition, the
pull-ups of Port 2 can be turned off for
open-drain operation.
9.1.1 Mode Registers
Each port has an associated mode register which
determines the port's functions and allows dynamic
change in port functions during program execu-
tion. Ports and mode registers are mapped into
the register file as shown in Figure 9-1.
Because of their close association, ports and mode
registers are treated like any other general-pur-
pose register. There are no special instructions
for port manipulation; any instruction that
addresses a register can address the ports. Data
can be directly accessed in the port register,
with no extra moves.
DEC
248
247
246
4
3
2
o
PORTS 0-1 MODE
PORT 3 MODE
PORT 2 MODE
PORT 3
PORT 2
PORT 1
PORTO
HEX IDENTIFIERS
Fa
P01M
F7
P3M
F6 P2M
04
03 P3
02
P2
01 P1
00 PO
Figure 9-1. I/O Port and Port Mode Registers
Chapter 9
1/0
Ports
9.1.2 Input and Output Registers
Each bit of Ports 0, 1, and 2 has an input regis-
ter, an output register, associated buffer, and
control logic. Since there are separate input and
output registers associated with each port, writ-
ing to bits defined as inputs stores the data in
the output register. This data cannot be read as
long as the bits are defined as inputs. However,
if the bits are reconfigured as output, the data
stored in the output register is reflected on the
output pins and can then be read. This mechanism
allows the user to initialize the outputs prior to
driving their loads.
Since port inputs are asynchronous to the Z8' s
internal clock, a Read operation could occur
during an input transition. In this case, the
logic level might be uncertain--somewhere between
a logic 1 and O. To eliminate this met a-stab Ie
condition, the Z8 latches the input data two clock
periods prior to the execution of the current
instruction. The input register uses these two
clock periods to stabilize to a legitimate logic
level before the instruction reads the data.
9.2 PORT 0
This section deals only with the I/O operation of
Port O. Refer to Sections 6.2 and 7.2 for a
description of the port's external memory inter-
face operation.
Port 0 is a general I/O port. Bits within each
nibble can be independently programmed as inputs,
outputs or address lines. Figure 9-2 shows a
block diagram of Port O. This diagram also
applies to Ports 1 and 2.
3047-063
9-1