ZiLOG System 8000 Hardware Reference Manual page 35

CPU Zilog
CPU
3.3.3. Offboard I/O:
All I/O addresses from 0 to FF80 and
even I/O addresses from FF80 through FFFF hexidecimal are
mapped offboard and can be word addressable for all I/O
addresses and byte addressable for even or odd I/O addresses
for special and standard I/O. The offboard I/O devices with
even addresses are subject to the byte swap buffer on I/O
reads the same as the memory read byte transactions.
3.4. Reset, Interrupts and Traps
The Z800lA CPU supports three types of exceptions or condi-
tions that can alter the normal flow of program execution.
These are system reset, interrupts, and traps. Because the
CPU responds to these exceptions and conditions in a similar
manner, they are discussed together in the following para-
,graphs.
3.4.1. System Reset:
The system reset is generated from
the onboard power-up reset circuit or by the RESET button on
the System 8000 front panel. It overrides all other operat-
ing conditions in the CPU, including interrupts, traps, bus
requests, and stop requests. Upon system reset, the follow-
ing occurs:
1. All bits in the SCR are cleared.
2. The local memory space is enabled, the CPU jumps to
location 2 of segment 0 and reads the Flag and Control
Word register (FCW) • It then reads the 7-bit program
counter (PC) segment number from location 4. Next it
reads the l6-bit PC offset from location 6. The fol-
lowing CPU FETCH starts the program.
3. The MMU ONH bit (Dl) is disabled and main memory refer-
ences are direct and without MMU assistance. The mode
register, violation type register, and descriptor
selection counter are cleared on all MMUs. However,
the Master Enable flag in the MMUs is not reset to
zero.
4. The SEG USER bit (D2) is cleared to logic 0 and a non-
segmented USER is supported.
5. Parity and ECC Error NMI (D3) is cleared.
6. All receivers and transmitters of the SIOs (channels)
are disabled. All SIO control registers must be ini-
tialized. All SIO interrupts are disabled.
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