Cpu Pin Assignments (P2) - ZiLOG System 8000 Hardware Reference Manual

CPU
Zilog
Table 2-4. CPU pin Assignments (P2)
CPU
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ROW A
TXRTNO
TXDO
RTSO
DSRO
TXDl
RTSI
DSRI
TXD2
RTS2
DSR2
TXD3
RTS3
DSR3
TXD4
RTS4
DSR4
TXD5
RTS5
DSR5
TXD6
RTS6
DSR6
.TXD7
RTS7
DSR7
TXRTN3
TXRTN4
+5Vdc
-5Vdc
NOT USED
NOT USED
GND
ROW B
RXDO
CTSO
DTRO
RXDI
CTSI
DTRI
RXD2
CTS2
DTR2
RXD3
CTS3
DTR3
RXD4
CTS4
DTR4
RXD5
CTS5
DTR5
RXD6
CTS6
DTR6
RXD7
CTS7
DTR7
TXRTN5
TXRTN6
TXRTN7
+5Vdc
-5Vdc
NOT USED
NOT USED
GND
ROW C
DATAO
DATAl
DATA2
GND
DATA3
DATA4
GND
DATA5
DATA6
DATA?
GND
DATA STROBE/ DATA STROBE-
NOT USED
TXRTNI
GND
D.D./ ACKNOWLEDGE-
BUSY-
TXRTN2
GND
IF VALID/ FAULT-
ON-LINE/ SELECT
F.P. BUSACK INDICATOR
F.P. POWER-ON INDICATOR (GND)
F.P. NORMAL INDICATOR
NMI SWITCH (NORMALLY CLOSED)
NMI SWITCH (NORMALLY
OPEN)
SWITCH RESET
F.P. INDICATOR V+ (+5Vdc)
-5Vdc
NOT USED
NOT USED
GND
NOTE: Pins
30
A,B,and C are connected to +12Vdc on the ZBI.
Table 2-5 lists the signal definitions for the CPU I/O bus.
2-3 Zilog
2-3