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CPU
Zilog
CPU
respond
with
a I6-bit word containing the byte data.
(See
byte swap buffer Para.3.2.4.3)
3.2.4.2
Byte
Write:
For
a
local
memory
write,
the
Read/Write (R/W) line is low and either the odd or even bank
of memory is enabled by the address bit
AD.
If
Arr
is
high,
the
odd
bank
is enabled, if low the even bank is enabled.
The Z800IA CPU duplicates the byte data on
both
halves
of
the
CPU
address bus when writing a byte of data to memory.
Therefore, the memory can pick off
the
byte
operand
from
either
half
of the bus by enabling the even or odd bank of
memory contingent on the least significant address bit AO.
3.2.4.3
Byte Swap Buffer:
under ZBI
specification,
during
byte transactions, only the low-order odd half of the system
bus, ADO-AD?,
can
be
used.
The
ZBI
bus
specification
requires that all byte operands be read on the low-order odd
half of the system bus regardless
of
their
address.
For
byte
reads with odd addresses or byte writes that duplicate
the data on both halves of the bus, this is not
a
problem.
However,
byte
reads
with
even addresses require that the
byte operand be placed on the high-order even
half
of
the
CPU address/data bus.
A byte swap buffer is activated
on
byte
reads
with
even
addresses
to
duplicate the byte data on both halves of the
CPU's internal address data bus.
This ensures that the byte
operand
will
appear
on
the
high-order
even half of the
Z800IA CPU internal bus on an even address byte read
memory
transaction.
The byte-swap buffer is totally transparent to
the operating system and user.
3.3.
I/O Addressing
The Z800IA CPU's input/output addresses are
represented
as
Ih-bit
words
that
reference either byte or word operands.
Two separate I/O address spaces, Standard
I/O
and
Special
I/O, are accessed through a separate set of I/O instructions
which can be executed only when the Z800IA
CPU
is
in
the
system
mode.
The
standard I/O instructions transfer data
between the CPU and onboard and offboard peripheral devices.
Special I/O instructions transfer data beween the ZaOOIA CPU
and the three Z8010A MMUs for
memory management.
3-5
Zilog
3-5
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